verilog怎么函数调用

verilog函数调用实例。
module comb15 (A, B, CIN, S, COUT);
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input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
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wire [1:0] S0, S1, S2, S3;
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function signed [1:0] ADD;
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input A, B, CIN;
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reg S, COUT;
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begin
S = A ^ B ^ CIN;
COUT = (A&B) | (A&CIN) | (B&CIN);
ADD = {COUT, S};
end
endfunction
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assign S0 = ADD (A[0], B[0], CIN),
S1 = ADD (A[1], B[1], S0[1]),
S2 = ADD (A[2], B[2], S1[1]),
S3 = ADD (A[3], B[3], S2[1]),
S = {S3[0], S2[0], S1[0], S0[0]},
COUT = S3[1];
endmodule